1. Field of the Invention
The present invention relates to flash memory technology, and more particularly to techniques for suppressing leakage in block-based flash memory devices.
2. Description of Related Art
Flash memory includes memory cells that store charge between the channel and gate of a field effect transistor. The charge stored affects the threshold voltage of the transistor. Changes in the threshold voltage due to the stored charge can be sensed to indicate data stored in the memory cell. One type of charge storage cell is known as a floating gate memory cell, which stores charge on an electrically conductive layer between the channel and gate. Another type of charge storage cell is referred to as a charge trapping memory cell, which uses a dielectric layer in place of the floating gate.
A memory cell can be programmed using various biasing techniques such as Fowler Nordheim (FN) tunneling, Channel Hot Electron (CHE), etc. The programming operation increases the threshold voltage of the memory cell.
A memory cell can be erased by applying a bias to induce hole tunneling into the charge storage layer, or to induce electron tunneling from the charge storage layer. The erase operation decreases the threshold voltage of the memory cell.
In a flash memory device, memory cells in an array are grouped into blocks, and memory cells in each block are erased together. Thus, in order to erase a memory cell in a block, all the memory cells in that block must also be erased. Consequently, an erase operation in a flash device is generally a slower process than a program operation.
Flash memory devices can suffer from the problem of over-erasure of the memory cells. When a block of memory cells is erased, some of the memory cells will have a lower threshold voltage than others. Over-erasure occurs if, during the erasing step, too many electrons are removed from the charge storage layer. This can leave a slight positive charge, which biases the memory cell slightly on, such that the memory cell is operating in depletion mode. This results in the memory cell conducting leakage current, even when it is not accessed. A number of over-erased cells along a given bit line can cause an accumulation of leakage current sufficient to cause a false reading of a selected memory cell sharing the same bit line.
For example, in a NOR architecture, drains of a number of memory cells are coupled together to a common bit line. If one or more memory cells has been over-erased, those memory cells will cause leakage current to flow on the common bit line, even when the cell is not directly accessed. During a read operation of a selected memory cell, the leakage current flowing on the common bit line due to the over-erased cell(s) can cause the current on the bit line to be high enough that the selected memory cell falsely appears to be erased.
It is therefore desirable to provide flash memory devices and methods for operating which address the issues caused by over-erased cells.